The most often used circuit carriers are copper-foil covered organic insulator plates. From these wiring lines can be created using subtractive technology. The manufacturing technology of Printed Wiring Board allows the realization of multilayer circuits with metallized vias and laminated layers.

Nowadays the increase of integration is a very important aspect. Integrated circuits usually have more than 500 terminals. BGA ICs appeared, where many bumps are very close to each other. Because the need of insulation distance in fine pitch BGA, not all connections can be placed in one layer, that is why vias have to be applied. If it is possible these connections have to be placed out of the pad. However this arrangement worsens the place-capacity of the surface, because bottom and inner wirings are restricted. A remedy of this is to use stacked vias and pads placed on vias. This is the so-called via on pad. In this case the terminals of the IC are placed on these microvias so thus the contact with inner layers is realized.

Mikrovia in flip chip Via-on pad

These microvias depending on the IC layout can be as small as 80 µm to keep the insulation distance belonged to the adjacent terminals between vias. The small diameter and cross-section are realized by laser. Using general PWB manufacturing vias are metallized (electrodeposited). Via cannot be deep correlating to its diameter otherwise the metallization might not to be correct. Thus the thickness of the carrier has to be decreased so that the via spans to lower layers. It can be realized by using organic insulator foils. Hereby the size of discrete elements and the carrier decreased.

HDI wiring of circuit substrates can be built up with general film technology. Multilayer wiring can be realized by Sequential Build Up (SBU) technology in case of laminated carriers. The point of the method is that the layers are built up on each other and not discrete multilayer substrates are laminated. The core board can be insulator coated copper foil or aramid fiber enhanced epoxy resin.

With an SBU process, conductor and dielectric layers are formed one after another, stacked on the previous layers. Normally build-up layers are formed on both sides of a core board, which itself is a printed wiring board. SBU layers have higher thermal expansion than core board created with general technology because of high density interconnection. That is why build-up layers are formed symmetrically on both sides of a core board. On the figure below a 3-4-3 construction can be seen, where 4 is the number of core board layers, 3 is the number of build-up layers.

A 3-4-3 construction build-up substrate

The CIP (Chip in Polymer) technology is based on the embedding of thin chips into the build-up layers of a printed circuit board (PCB) thus the terminals need less place. The principle structure is shown in figure below.

lC chip buried in polymer

There is two technology to bury chips on the figure below.

Chip embedded by liquid photo-dielectric Embedding by lamination into a RCC layer

Properties of build-up (SBU) technology:

• Excellent insulation (ε=3,9-4,8 As/Vm),
• less good heat conductor (0,35 W/mK),
• low prime cost,
• very fine patterning,
• compatible with PWB manufacturing machines,
• passive and active element can be buried.